Overview
Flight software (FSW) engineers write the software that runs on a spacecraft's radiation‐hardened processor. Their work includes attitude control loops, fault‐protection algorithms, command and telemetry managers, payload sequencers, memory scrubbers, and uplink/downlink protocol stacks.
Responsibilities
- Write software for radiation‐hardened processors under real‐time operating systems such as VxWorks 653, RTEMS, FreeRTOS, or NASA's Core Flight System (cFS).
- Design and implement attitude‐control loops, fault‐protection algorithms, command and telemetry managers, payload sequencers, memory scrubbers, and uplink/downlink protocol stacks.
- Use formal‐methods techniques (SPARK Ada proofs, Frama‐C static analysis), model‐based design (Simulink/Stateflow auto‐code generation), and rigorous unit and integration testing (GMock, Cantata++, VectorCAST).
- Maintain traceability from requirements to code using DOORS and conduct peer reviews and configuration‐management tasks.
- Conduct hardware‐in‐the‐loop simulation and validate software against flight‐hardware models.
Qualifications
- Bachelor's degree in Computer Science, Software Engineering, Electrical Engineering, or a related field.
- Master's degree in Real‐Time Embedded Systems, Computer Engineering, or Aerospace Engineering is preferred.
- Proficiency in C or C++; experience with Ada/SPARK is a plus.
- Hands‐on experience programming for real‐time operating systems (VxWorks 653, RTEMS, FreeRTOS, cFS).
- Familiarity with formal‐verification tools, model‐based code generation, and static‐analysis tools.
- Experience with DOORS traceability, unit/integration testing frameworks (GMock, Cantata++, VectorCAST), and HIL simulation.
- Minimum 3–5 years of relevant industry or research experience; a strong senior/lead background (5+ years) is desirable.
Key Skills
- Embedded C/C++ programming
- Real‐time scheduler theory (Rate‐Monotonic, EDF)
- Formal verification (SPARK Ada, Frama‐C)
- Model‐based design and automatic code generation (Simulink/Stateflow)
- Static analysis and software‐testing tools (VectorCAST, Cantata++, LDRA)
- Hardware‐in‐the‐loop simulation
- DOORS traceability and configuration‐management
- Space communication protocols (CCSDS, SpaceWire RMAP)
Salary (U.S.)
Entry level (0–3 years): $110 000. Median (4–8 years): $168 000. Senior (9+ years): $250 000. (US‐centric estimates; international compensation varies.)
Global Opportunities
- NASA (USA)
- ESA/ESTEC (Europe)
- CNES (France)
- DLR (Germany)
- ISRO (India)
- JAXA (Japan)
- MDA Space (Canada)
- KARI (South Korea)
- Satrec Initiative (South Korea)
Reality Check
Good fit if:
- You find formal verification or proof‐of‐correctness intellectually rewarding.
- You are comfortable doing code review on safety‐critical C where a single missing bounds check could destroy a mission.
- You enjoy working at the boundary of software and hardware—reading datasheets, writing device drivers, and debugging with a logic analyser.
Bad fit if:
- You want modern web‐style development practices; this role has no Docker, no CD pipelines, and 18‐month qualification cycles for a 200‐line change.
- You find process documentation (SRS, SDD, test reports per ECSS‐E‐ST‐40C or NASA‐STD‐8739.8) bureaucratic and demotivating.
- You are motivated primarily by performance optimisation; FSW correctness constraints often prevent elegant algorithmic solutions.
Flight Software Engineer employer: UNKNOWN
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