SOC Design Engineer: RTL & IP Integration, Visa Friendly in Cambridge

SOC Design Engineer: RTL & IP Integration, Visa Friendly in Cambridge

Cambridge Full-Time 49500 - 60500 $ / year (est.) On-site
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At a Glance

  • Tasks: Design and integrate cutting-edge System on Chips with innovative IP blocks.
  • Company: Join Arm, a leader in tech innovation based in Cambridge.
  • Benefits: Competitive salary, Visa sponsorship, and opportunities for professional growth.
  • Other info: Mentorship opportunities and a collaborative work environment.
  • Why this job: Be part of a dynamic team shaping the future of technology.
  • Qualifications: Experience in RTL design and a passion for hardware engineering.

The predicted salary is between 49500 - 60500 $ per year.

Arm's Cambridge-based SOC Design Engineer role focuses on developing System on Chips by integrating IP blocks such as CPU clusters, PCIe and memory interfaces.

You will draft micro-architecture specs, create RTL designs in Verilog/System Verilog, and collaborate with verification to meet timing and power goals.

You will participate in backend tasks like floor planning and timing closure, while contributing to design methodologies and mentoring teammates in a dynamic hardware team.

SOC Design Engineer: RTL & IP Integration, Visa Friendly in Cambridge employer: ARM

ARM in the Town of Cambridge is an exceptional employer that fosters a collaborative and inclusive work culture, making it an ideal place for professionals seeking to lead innovative AI projects. With a strong emphasis on employee growth and development, team members are encouraged to leverage their unique perspectives while contributing to strategic initiatives that drive efficiency and success. The vibrant local community and commitment to diversity further enhance the rewarding experience of working at ARM.

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Contact Details:

ARM Recruitment Team

We think you need these skills to ace SOC Design Engineer: RTL & IP Integration, Visa Friendly in Cambridge

System on Chip (SoC) Design
RTL Design
Verilog
SystemVerilog
Micro-architecture Specification
IP Integration
Timing Closure