At a Glance
- Tasks: Create test plans and build verification environments for cutting-edge IP designs.
- Company: Join Apple, a leader in innovation and technology.
- Benefits: Competitive salary, health benefits, and opportunities for professional growth.
- Other info: Dynamic work environment with a focus on collaboration and innovation.
- Why this job: Be part of groundbreaking projects that shape the future of technology.
- Qualifications: Strong background in design verification methodology and experience with SystemVerilog/UVM.
The predicted salary is between 49500 - 60500 $ per year.
Apple is seeking an outstandingly hardworking design verification engineer to develop pre-silicon verification for IP designs.
You will craft test plans, build scalable verification environments, and drive regression analysis using System Verilog/UVM and LLMs to improve quality and efficiency.
You will work on first silicon for IP blocks, develop verification plans, and report DV progress with metrics across bugs and coverage.
A strong background in DV methodology is required.
Design Verification Engineer – SoC Pre-Silicon (SystemVerilog/UVM) in Melbourne employer: Apple Inc.
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